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HPCA
2004
IEEE
14 years 9 months ago
Signature Buffer: Bridging Performance Gap between Registers and Caches
Data communications between producer instructions and consumer instructions through memory incur extra delays that degrade processor performance. In this paper, we introduce a new...
Lu Peng, Jih-Kwon Peir, Konrad Lai
ISCA
2010
IEEE
305views Hardware» more  ISCA 2010»
14 years 1 months ago
Rethinking DRAM design and organization for energy-constrained multi-cores
DRAM vendors have traditionally optimized the cost-perbit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, wher...
Aniruddha N. Udipi, Naveen Muralimanohar, Niladris...
FSE
2009
Springer
159views Cryptology» more  FSE 2009»
14 years 3 months ago
Intel's New AES Instructions for Enhanced Performance and Security
The Advanced Encryption Standard (AES) is the Federal Information Processing Standard for symmetric encryption. It is widely believed to be secure and efficient, and is therefore b...
Shay Gueron
CASES
2006
ACM
14 years 2 months ago
Adapting compilation techniques to enhance the packing of instructions into registers
The architectural design of embedded systems is becoming increasingly idiosyncratic to meet varying constraints regarding energy consumption, code size, and execution time. Tradit...
Stephen Hines, David B. Whalley, Gary S. Tyson
TC
2008
13 years 8 months ago
Exploiting In-Memory and On-Disk Redundancy to Conserve Energy in Storage Systems
Abstract--Today's storage systems place an imperative demand on energy efficiency. A storage system often places single-rotationrate disks into standby mode by stopping them f...
Jun Wang, Xiaoyu Yao, Huijun Zhu