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ICPADS
2006
IEEE
14 years 1 months ago
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edw...
ISCA
1998
IEEE
104views Hardware» more  ISCA 1998»
13 years 12 months ago
Selective Eager Execution on the PolyPath Architecture
Control-flow misprediction penalties are a major impediment to high performance in wide-issue superscalar processors. In this paper we present Selective Eager Execution (SEE), an ...
Artur Klauser, Abhijit Paithankar, Dirk Grunwald
SSDBM
2010
IEEE
142views Database» more  SSDBM 2010»
13 years 5 months ago
Efficient and Adaptive Distributed Skyline Computation
Skyline queries have attracted considerable attention over the last few years, mainly due to their ability to return interesting objects without the need for user-defined scoring f...
George Valkanas, Apostolos N. Papadopoulos
ICCD
2008
IEEE
126views Hardware» more  ICCD 2008»
14 years 2 months ago
Accelerating search and recognition with a TCAM functional unit
Abstract— World data is increasing rapidly, doubling almost every three years[1][2]. To comprehend and use this data effectively, search and recognition (SR) applications will de...
Atif Hashmi, Mikko Lipasti
DPD
2002
125views more  DPD 2002»
13 years 7 months ago
Parallel Mining of Outliers in Large Database
Data mining is a new, important and fast growing database application. Outlier (exception) detection is one kind of data mining, which can be applied in a variety of areas like mon...
Edward Hung, David Wai-Lok Cheung