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ISCA
1996
IEEE
130views Hardware» more  ISCA 1996»
13 years 11 months ago
Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors
Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to addres...
Mark Horowitz, Margaret Martonosi, Todd C. Mowry, ...
DATE
2010
IEEE
165views Hardware» more  DATE 2010»
14 years 13 days ago
Multicore soft error rate stabilization using adaptive dual modular redundancy
— The use of dynamic voltage and frequency scaling (DVFS) in contemporary multicores provides significant protection from unpredictable thermal events. A side effect of DVFS can ...
Ramakrishna Vadlamani, Jia Zhao, Wayne P. Burleson...
CHES
2004
Springer
216views Cryptology» more  CHES 2004»
13 years 11 months ago
Efficient Countermeasures against RPA, DPA, and SPA
In the execution on a smart card, side channel attacks such as simple power analysis (SPA) and the differential power analysis (DPA) have become serious threat [15]. Side channel a...
Hideyo Mamiya, Atsuko Miyaji, Hiroaki Morimoto
FCCM
2004
IEEE
130views VLSI» more  FCCM 2004»
13 years 11 months ago
Hyperreconfigurable Architectures for Fast Run Time Reconfiguration
Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or structure to suit changing needs of a computation during run time. The increasing...
Sebastian Lange, Martin Middendorf
MCS
2010
Springer
13 years 9 months ago
Dynamic Selection of Ensembles of Classifiers Using Contextual Information
In a multiple classifier system, dynamic selection (DS) has been used successfully to choose only the best subset of classifiers to recognize the test samples. Dos Santos et al...
Paulo Rodrigo Cavalin, Robert Sabourin, Ching Y. S...