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HPCA
2005
IEEE
14 years 9 months ago
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
Aamer Jaleel, Bruce L. Jacob
IPPS
2007
IEEE
14 years 2 months ago
Determining the Minimum Energy Consumption using Dynamic Voltage and Frequency Scaling
While improving raw performance is of primary interest to most users of high-performance computers, energy consumption also is a critical concern. Some microprocessors allow volta...
Min Yeol Lim, Vincent W. Freeh
MSS
2007
IEEE
109views Hardware» more  MSS 2007»
14 years 2 months ago
GreenStor: Application-Aided Energy-Efficient Storage
The volume of online data content has shown an un­ precedented growth in recent years. Fueling this growth are new federal regulations which warrant longer data re­ tention and ...
NagaPramod Mandagere, Jim Diehl, David Hung-Chang ...
ISCA
2006
IEEE
169views Hardware» more  ISCA 2006»
14 years 2 months ago
Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
Chuanjun Zhang
ICCAD
2010
IEEE
125views Hardware» more  ICCAD 2010»
13 years 6 months ago
Peak current reduction by simultaneous state replication and re-encoding
Reducing circuit's peak current plays an important role in circuit reliability in deep sub-micron era. For sequential circuits, it is observed that the peak current has a str...
Junjun Gu, Gang Qu, Lin Yuan, Qiang Zhou