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ISCA
2005
IEEE
115views Hardware» more  ISCA 2005»
15 years 8 months ago
RENO - A Rename-Based Instruction Optimizer
RENO is a modified MIPS R10000 register renamer that uses map-table “short-circuiting” to implement dynamic versions of several well-known static optimizations: move eliminat...
Vlad Petric, Tingting Sha, Amir Roth
MICRO
2005
IEEE
110views Hardware» more  MICRO 2005»
15 years 8 months ago
Scalable Store-Load Forwarding via Store Queue Index Prediction
Conventional processors use a fully-associative store queue (SQ) to implement store-load forwarding. Associative search latency does not scale well to capacities and bandwidths re...
Tingting Sha, Milo M. K. Martin, Amir Roth
134
Voted
ASPDAC
2008
ACM
154views Hardware» more  ASPDAC 2008»
15 years 4 months ago
Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...
Swaroop Ghosh, Kaushik Roy
126
Voted
ICCAD
2009
IEEE
135views Hardware» more  ICCAD 2009»
15 years 8 days ago
Enhanced reliability-aware power management through shared recovery technique
While Dynamic Voltage Scaling (DVS) remains as a popular energy management technique for real-time embedded applications, recent research has identified significant and negative i...
Baoxian Zhao, Hakan Aydin, Dakai Zhu
117
Voted
DAC
2005
ACM
16 years 3 months ago
Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions
While performance specifications are verified before sign-off for a modern nanometer scale design, extensive application of optical proximity correction substantially alters the l...
Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Denni...