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ISCA
2006
IEEE
182views Hardware» more  ISCA 2006»
15 years 8 months ago
Cooperative Caching for Chip Multiprocessors
This paper presents CMP Cooperative Caching, a unified framework to manage a CMP’s aggregate on-chip cache resources. Cooperative caching combines the strengths of private and ...
Jichuan Chang, Gurindar S. Sohi
ISPD
2006
ACM
90views Hardware» more  ISPD 2006»
15 years 8 months ago
Fast buffer insertion considering process variations
Advanced process technologies call for a proactive consideration of process variations in design to ensure high parametric timing yield. Despite of its popular use in almost any h...
Jinjun Xiong, Lei He
MICRO
2003
IEEE
116views Hardware» more  MICRO 2003»
15 years 7 months ago
Universal Mechanisms for Data-Parallel Architectures
Data-parallel programs are both growing in importance and increasing in diversity, resulting in specialized processors targeted at specific classes of these programs. This paper ...
Karthikeyan Sankaralingam, Stephen W. Keckler, Wil...
HPCA
2011
IEEE
14 years 6 months ago
MOPED: Orchestrating interprocess message data on CMPs
Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization...
Junli Gu, Steven S. Lumetta, Rakesh Kumar, Yihe Su...
ISCA
2012
IEEE
261views Hardware» more  ISCA 2012»
13 years 4 months ago
RAIDR: Retention-aware intelligent DRAM refresh
Dynamic random-access memory (DRAM) is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent loss of data. These refresh operation...
Jamie Liu, Ben Jaiyen, Richard Veras, Onur Mutlu