93 search results - page 18 / 19 » Improving Memory-System Performance of Sparse Matrix-Vector ... |
HPCA
2003
IEEE
14 years 8 months ago
2003
IEEE
Although caches for decades have been the backbone of the memory system, the speed gap between CPU and main memory suggests their augmentation with prefetching mechanisms. Recentl...
MICRO
2002
IEEE
14 years 18 days ago
2002
IEEE
Register integration (or just integration) is a register renaming discipline that implements instruction reuse via physical register sharing. Initially developed to perform squash...
SOSP
1997
ACM
13 years 9 months ago
1997
ACM
Low-latency remote-write networks, such as DEC’s Memory Channel, provide the possibility of transparent, inexpensive, large-scale shared-memory parallel computing on clusters of...
MSWIM
2003
ACM
14 years 28 days ago
2003
ACM
This paper presents ARC (Adaptive Range Control), a communication range control mechanism using directional antennas to be implemented across multiple layers. ARC uses directional...
MICRO
1997
IEEE
13 years 12 months ago
1997
IEEE
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...