315 search results - page 39 / 63 » Improving Performance by Branch Reordering |
HPCA
2007
IEEE
14 years 9 months ago
2007
IEEE
3D integration technology greatly increases transistor density while providing faster on-chip communication. 3D implementations of processors can simultaneously provide both laten...
ICCAD
2005
IEEE
14 years 5 months ago
2005
IEEE
We present a new hardware synthesis methodology for guarded atomic actions (or rules), which satisfies performance-related scheduling specifications provided by the designer. The ...
ICCD
2000
IEEE
14 years 5 months ago
2000
IEEE
In superscalar architectures, out-of-order issue mechanisms increase performance by dynamically rescheduling instructions that cannot be statically reordered by the compiler. Whil...
SC
2000
ACM
14 years 1 months ago
2000
ACM
The performance of the MPI’s collective communications is critical in most MPI-based applications. A general algorithm for a given collective communication operation may not giv...
ICS
1999
Tsinghua U.
14 years 1 months ago
1999
Tsinghua U.
Programming languages that provide multidimensional arrays and a flat linear model of memory must implement a mapping between these two domains to order array elements in memory....