328 search results - page 18 / 66 » Improving Performance of Small On-Chip Instruction Caches |
HPCA
2004
IEEE
14 years 8 months ago
2004
IEEE
Recent research suggests that there are large variations in a cache's spatial usage, both within and across programs. Unfortunately, conventional caches typically employ fixe...
CASES
2008
ACM
13 years 9 months ago
2008
ACM
Dynamic binary translators (DBT) have recently attracted much attention for embedded systems. The effective implementation of DBT in these systems is challenging due to tight cons...
ECRTS
2008
IEEE
14 years 2 months ago
2008
IEEE
Procedure Positioning is a well known compiler optimization aiming at the improvement of the instruction cache behavior. A contiguous mapping of procedures calling each other freq...
ISLPED
2003
ACM
14 years 27 days ago
2003
ACM
Many of the recently proposed techniques to reduce power consumption in caches introduce an additional level of nondeterminism in cache access latency. Due to this additional late...
JEC
2006
13 years 7 months ago
2006
This paper shows that even very small data caches, when split to serve data streams exhibiting temporal and spatial localities, can improve performance of embedded applications wit...