328 search results - page 19 / 66 » Improving Performance of Small On-Chip Instruction Caches |
ICS
2009
Tsinghua U.
14 years 2 months ago
2009
Tsinghua U.
The L2 cache is commonly managed using LRU policy. For workloads that have a working set larger than L2 cache, LRU behaves poorly, resulting in a great number of less reused lines...
IEEEPACT
2007
IEEE
14 years 1 months ago
2007
IEEE
Distinguishing transient blocks from frequently used blocks enables servicing references to transient blocks from a small fully-associative auxiliary cache structure. By inserting...
WWW
2007
ACM
14 years 8 months ago
2007
ACM
Online auction sites have very specific workloads and user behavior characteristics. Previous studies on workload characterization conducted by the authors showed that i) bidding a...
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
PLDI
2005
ACM
14 years 1 months ago
2005
ACM
Code placement techniques have traditionally improved instruction fetch bandwidth by increasing instruction locality and decreasing the number of taken branches. However, traditio...