328 search results - page 36 / 66 » Improving Performance of Small On-Chip Instruction Caches |
ISCA
2002
IEEE
14 years 15 days ago
2002
IEEE
An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of th...
ISCA
2003
IEEE
14 years 25 days ago
2003
IEEE
Despite their superior performance for multimedia applications, vector processors have three limitations that hinder their widespread acceptance. First, the complexity and size of...
IPPS
1998
IEEE
13 years 11 months ago
1998
IEEE
In this paper, we present several novel strategies to improve software controlled cache utilization, so as to achieve lower power requirements for multi-media and signal processin...
HPCA
2004
IEEE
14 years 8 months ago
2004
IEEE
Modern out-of-order processors tolerate long latency memory operations by supporting a large number of inflight instructions. This is particularly useful in numerical applications...
ASAP
2007
IEEE
13 years 11 months ago
2007
IEEE
Software-based, fine-grain control flow integrity (CFI) validation technique has been proposed to enforce control flow integrity of program execution. By validating every indirect...