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» Improving Performance of Small On-Chip Instruction Caches
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CF
2006
ACM
14 years 1 months ago
Exploiting locality to ameliorate packet queue contention and serialization
Packet processing systems maintain high throughput despite relatively high memory latencies by exploiting the coarse-grained parallelism available between packets. In particular, ...
Sailesh Kumar, John Maschmeyer, Patrick Crowley
HPCA
2000
IEEE
13 years 12 months ago
Impact of Chip-Level Integration on Performance of OLTP Workloads
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
Luiz André Barroso, Kourosh Gharachorloo, A...
MSS
2007
IEEE
83views Hardware» more  MSS 2007»
14 years 1 months ago
The RAM Enhanced Disk Cache Project (REDCAP)
This paper presents the RAM Enhanced Disk Cache Project, REDCAP, a new cache of disk blocks which reduces the read I/O time by using a small portion of the main memory. The essent...
Pilar Gonzalez-Ferez, Juan Piernas, Toni Cortes
ASPLOS
2004
ACM
14 years 1 months ago
Continual flow pipelines
Increased integration in the form of multiple processor cores on a single die, relatively constant die sizes, shrinking power envelopes, and emerging applications create a new cha...
Srikanth T. Srinivasan, Ravi Rajwar, Haitham Akkar...
CSREAEEE
2006
120views Business» more  CSREAEEE 2006»
13 years 9 months ago
Object Caching Model for Cell Phone Mobile Database
- Inherent limitations of mobile computing environment such as limited bandwidth, limited resourced mobile phones, and instability of wireless environment require summarized mobile...
Khubaib Ahmed Qureshi