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» Improving Performance of Small On-Chip Instruction Caches
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ICCAD
2001
IEEE
272views Hardware» more  ICCAD 2001»
14 years 4 months ago
NetBench: A Benchmarking Suite for Network Processors
— In this study we introduce NetBench, a benchmarking suite for network processors. NetBench contains a total of 9 applications that are representative of commercial applications...
Gokhan Memik, William H. Mangione-Smith, Wendong H...
ASYNC
1998
IEEE
122views Hardware» more  ASYNC 1998»
13 years 11 months ago
A Fast Asynchronous Huffman Decoder for Compressed-Code Embedded Processors
This paper presents the architecture and design of a high-performance asynchronous Huffman decoder for compressed-code embedded processors. In such processors, embedded programs a...
Martin Benes, Steven M. Nowick, Andrew Wolfe
PLDI
1999
ACM
13 years 12 months ago
Cache-Conscious Structure Layout
Hardware trends have produced an increasing disparity between processor speeds and memory access times. While a variety of techniques for tolerating or reducing memory latency hav...
Trishul M. Chilimbi, Mark D. Hill, James R. Larus
ICCD
2003
IEEE
107views Hardware» more  ICCD 2003»
14 years 4 months ago
Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches
Embedded processors like Intel’s XScale use dynamic branch prediction to improve performance. Due to the presence of context switches, the accuracy of these predictors is reduce...
Sudeep Pasricha, Alexander V. Veidenbaum
VLSID
2006
IEEE
142views VLSI» more  VLSID 2006»
14 years 8 months ago
Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors
- Security protocols, such as IPSec and SSL, are being increasingly deployed in the context of networked embedded systems. The resource-constrained nature of embedded systems and, ...
Nachiketh R. Potlapally, Srivaths Ravi, Anand Ragh...