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» Improving Performance of Small On-Chip Instruction Caches
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TON
2002
86views more  TON 2002»
13 years 7 months ago
Efficient randomized web-cache replacement schemes using samples from past eviction times
The problem of document replacement in web caches has received much attention in recent research, and it has been shown that the eviction rule "replace the least recently used...
Konstantinos Psounis, Balaji Prabhakar
ISCA
2005
IEEE
98views Hardware» more  ISCA 2005»
14 years 1 months ago
Techniques for Efficient Processing in Runahead Execution Engines
Runahead execution is a technique that improves processor performance by pre-executing the running application instead of stalling the processor when a long-latency cache miss occ...
Onur Mutlu, Hyesoon Kim, Yale N. Patt
IPPS
2000
IEEE
13 years 12 months ago
A Mechanism for Speculative Memory Accesses Following Synchronizing Operations
In order to reduce the overhead of synchronizing operations of shared memory multiprocessors, this paper proposes a mechanism, named specMEM, to execute memory accesses following ...
Takayuki Sato, Kazuhiko Ohno, Hiroshi Nakashima
ICCD
2005
IEEE
108views Hardware» more  ICCD 2005»
14 years 4 months ago
Methods for Modeling Resource Contention on Simultaneous Multithreading Processors
Simultaneous multithreading (SMT) seeks to improve the computation throughput of a processor core by sharing primary resources such as functional units, issue bandwidth, and cache...
Tipp Moseley, Dirk Grunwald, Joshua L. Kihm, Danie...
DAC
2003
ACM
14 years 8 months ago
Embedded intelligent SRAM
Many embedded systems use a simple pipelined RISC processor for computation and an on-chip SRAM for data storage. We present an enhancement called Intelligent SRAM (ISRAM) that co...
Prabhat Jain, G. Edward Suh, Srinivas Devadas