328 search results - page 51 / 66 » Improving Performance of Small On-Chip Instruction Caches |
ISCA
2000
IEEE
13 years 12 months ago
2000
IEEE
Reconfigurable hardware has the potential for significant performance improvements by providing support for application−specific operations. We report our experience with Chimae...
ISCA
2007
IEEE
14 years 1 months ago
2007
IEEE
Conventional load/store queues (LSQs) are an impediment to both power-efficient execution in superscalar processors and scaling to large-window designs. In this paper, we propose...
MICRO
2005
IEEE
14 years 1 months ago
2005
IEEE
We present the TM3270 media-processor, the latest TriMedia VLIW processor, tuned to address the performance demands of standard definition video processing, combined with embedded...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
LCPC
2005
Springer
14 years 1 months ago
2005
Springer
Programming network processors remains a challenging task since their birth until recently when high-level programming environments for them are emerging. By employing domain speci...