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» Improving Performance of Small On-Chip Instruction Caches
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MICRO
1995
IEEE
97views Hardware» more  MICRO 1995»
13 years 11 months ago
Improving CISC instruction decoding performance using a fill unit
Current superscalar processors, both RISC and CISC, require substantial instruction fetch and decode bandwidth to keep multiple functional units utilized. While CISC instructions ...
Mark Smotherman, Manoj Franklin
DAC
2010
ACM
13 years 7 months ago
Instruction cache locking using temporal reuse profile
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
Yun Liang, Tulika Mitra
SAMOS
2005
Springer
14 years 1 months ago
Flux Caches: What Are They and Are They Useful?
In this paper, we introduce the concept of flux caches envisioned to improve processor performance by dynamically changing the cache organization and implementation. Contrary to t...
Georgi Gaydadjiev, Stamatis Vassiliadis
HPCA
2005
IEEE
14 years 8 months ago
Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications
In this paper, we study the instruction cache miss behavior of four modern commercial applications (a database workload, TPC-W, SPECjAppServer2002 and SPECweb99). These applicatio...
Lawrence Spracklen, Yuan Chou, Santosh G. Abraham
TC
1998
13 years 7 months ago
Optimizing the Instruction Cache Performance of the Operating System
—High instruction cache hit rates are key to high performance. One known technique to improve the hit rate of caches is to minimize cache interference by improving the layout of ...
Josep Torrellas, Chun Xia, Russell L. Daigle