1045 search results - page 174 / 209 » Improving SHA-2 Hardware Implementations |
IEEEPACT
2006
IEEE
14 years 1 months ago
2006
IEEE
On machines with high-performance processors, the memory system continues to be a performance bottleneck. Compilers insert prefetch operations and reorder data accesses to improve...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
Vertex cache of programmable geometry processor The proposed architecture of vertex cache is divided into is proposed and implemented. The proposed vertex cache is pre-TnL vertex c...
ISLPED
2006
ACM
14 years 1 months ago
2006
ACM
Today’s superscalar microprocessors use large, heavily-ported physical register files (RFs) to increase the instruction throughput. The high complexity and power dissipation of ...
CODES
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper, we present a new architectural concept for network processors called FlexPath NP. The central idea behind FlexPath NP is to systematically map network processor (NP...
MSS
2005
IEEE
14 years 1 months ago
2005
IEEE
Obtaining consistent bandwidth with predictable latency from disk-based storage systems has proven difficult due to the storage system’s inability to understand Quality of Serv...