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» Improving SHA-2 Hardware Implementations
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ACSD
2005
IEEE
90views Hardware» more  ACSD 2005»
14 years 2 months ago
Improved Decomposition of STGs
Signal Transition Graphs (STGs) are a version of Petri nets for the specification of asynchronous circuit behaviour. It has been suggested to decompose such a specification as a...
Walter Vogler, Ben Kangsah
ITCC
2005
IEEE
14 years 2 months ago
A Parallelized Design for an Elliptic Curve Cryptosystem Coprocessor
In many applications a software implementation of ECC (Elliptic Curve Cryptography) might be inappropriate due to performance requirements, therefore hardware implementations are ...
Fabio Sozzani, Guido Bertoni, Stefano Turcato, Luc...
CCECE
2006
IEEE
14 years 2 months ago
Survey of Biological High Performance Computing: Algorithms, Implementations and Outlook Research
During recent years there has been an explosive growth of biological data coming from genome projects, proteomics, protein structure determination, and the rapid expansion in digi...
Nasreddine Hireche, J. M. Pierre Langlois, Gabriel...
DATE
2009
IEEE
159views Hardware» more  DATE 2009»
14 years 3 months ago
Design and implementation of a database filter for BLAST acceleration
— BLAST is a very popular Computational Biology algorithm. Since it is computationally expensive it is a natural target for acceleration research, and many reconfigurable archite...
Panagiotis Afratis, Constantinos Galanakis, Euripi...
ASPDAC
1999
ACM
113views Hardware» more  ASPDAC 1999»
14 years 1 months ago
An Efficient Iterative Improvement Technique for VLSI Circuit Partitioning Using Hybrid Bucket Structures
In this paper, we present a fast and efficient Iterative Improvement Partitioning (IIP) technique for VLSI circuits and hybrid bucket structures on its implementation. Due to thei...
C. K. Eem, J. W. Chong