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VLSISP
2011
358views Database» more  VLSISP 2011»
13 years 4 months ago
Accelerating Machine-Learning Algorithms on FPGAs using Pattern-Based Decomposition
Machine-learning algorithms are employed in a wide variety of applications to extract useful information from data sets, and many are known to suffer from superlinear increases in ...
Karthik Nagarajan, Brian Holland, Alan D. George, ...
DATE
2000
IEEE
82views Hardware» more  DATE 2000»
14 years 2 months ago
Constructive Library-Aware Synthesis Using Symmetries
In this paper a constructive library-aware multilevel logic synthesis approach using symmetries is described. It integrates the technology-independent and technologydependent stag...
Victor N. Kravets, Karem A. Sakallah
DAGM
2008
Springer
13 years 11 months ago
Sliding-Windows for Rapid Object Class Localization: A Parallel Technique
Abstract. This paper presents a fast object class localization framework implemented on a data parallel architecture currently available in recent computers. Our case study, the im...
Christian Wojek, Gyuri Dorkó, André ...
DATE
2009
IEEE
81views Hardware» more  DATE 2009»
14 years 4 months ago
ReSim, a trace-driven, reconfigurable ILP processor simulator
— Modern processors are becoming more complex and as features and application size increase, their evaluation is becoming more time-consuming. To date, design space exploration r...
Sotiria Fytraki, Dionisios N. Pnevmatikatos
MICRO
2008
IEEE
111views Hardware» more  MICRO 2008»
14 years 4 months ago
Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute buffer
It is well recognized that LRU cache-line replacement can be ineffective for applications with large working sets or non-localized memory access patterns. Specifically, in lastle...
Livio Soares, David K. Tam, Michael Stumm