1045 search results - page 91 / 209 » Improving SHA-2 Hardware Implementations |
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
- We describe a preprocessing step to fault diagnosis of an observed response obtained from a faulty chip. In this step, a fault model for diagnosing the observed response is selec...
DDECS
2009
IEEE
14 years 4 months ago
2009
IEEE
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...
ISCAS
2008
IEEE
14 years 4 months ago
2008
IEEE
Abstract— Beamforming (BF) for multiple-input multipleoutput (MIMO) wireless communications systems can improve the error rate performance by spatial separation of the transmitte...
ISCAS
2007
IEEE
14 years 4 months ago
2007
IEEE
— A flexible transport stream processor for DTV which is also designed under cost-effective consideration is proposed in this paper. A RISC micro-controller is allocated as the ...
SBACPAD
2007
IEEE
14 years 4 months ago
2007
IEEE
One way to exploit Thread Level Parallelism (TLP) is to use architectures that implement novel multithreaded execution models, like Scheduled DataFlow (SDF). This latter model pro...