75 search results - page 12 / 15 » Improving WCET by applying worst-case path optimizations |
ICPP
2007
IEEE
14 years 1 months ago
2007
IEEE
A self-organizing peer-to-peer system is built upon an application level overlay, whose topology is independent of underlying physical network. A well-routed message path in such ...
ISQED
2007
IEEE
14 years 29 days ago
2007
IEEE
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
HPCA
2009
IEEE
14 years 7 months ago
2009
IEEE
Several recent processor designs have proposed to enhance performance by increasing the clock frequency to the point where timing faults occur, and by adding error-correcting supp...
DATE
2010
IEEE
13 years 11 months ago
2010
IEEE
High-level synthesis has recently started to gain industrial acceptance, due to the improved quality of results and the multi-objective optimizations offered. One optimization area...
PE
2006
Springer
13 years 6 months ago
2006
Springer
In a multi-level cache such as those used for web caching, a hit at level l leads to the caching of the requested object in all intermediate caches on the reverse path (levels l -...