259 search results - page 6 / 52 » Improving coverage analysis and test generation for large de... |
ATS
2000
IEEE
13 years 12 months ago
2000
IEEE
We present a new test generation procedure for sequential circuits using newly traversed state and newly detected fault information obtained between successive iterations of vecto...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
The biggest obstacle in the formal verification of large designs is their very large state spaces, which cannot be handled even by techniques such as implicit state space travers...
ICCD
2002
IEEE
14 years 4 months ago
2002
IEEE
Low power design techniques have been employed for more than two decades, however an emerging problem is satisfying the test power constraints for avoiding destructive test and im...
ICTAI
2002
IEEE
14 years 12 days ago
2002
IEEE
In order to reduce the time-to-market and simplify gatelevel test generation for digital integrated circuits, GAbased functional test generation techniques are proposed for behavi...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
Despite the growing research effort in formal verification, constraint-based random simulation remains an integral part of design validation, especially for large design componen...