71 search results - page 6 / 15 » Improving memory bank-level parallelism in the presence of p... |
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Due to shared cache contentions and interconnect delays, data prefetching is more critical in alleviating penalties from increasing memory latencies and demands on Chip-Multiproce...
IPPS
2003
IEEE
14 years 19 days ago
2003
IEEE
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
TJS
2008
13 years 7 months ago
2008
Abstract. Traditionally, loop nests are fused only when the data dependences in the loop nests are not violated. This paper presents a new loop fusion algorithm that is capable of ...
ASPLOS
2010
ACM
14 years 1 months ago
2010
ACM
A traditional fixed-function graphics accelerator has evolved into a programmable general-purpose graphics processing unit over the last few years. These powerful computing cores...
IEEEPACT
1999
IEEE
13 years 11 months ago
1999
IEEE
Image processing applications tend to access their data non-sequentially and reuse that data infrequently. As a result, they tend to perform poorly on conventional memory systems ...