1001 search results - page 38 / 201 » Improving memory hierarchy performance for irregular applica... |
133
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ICCAD
2005
IEEE
16 years 3 months ago
2005
IEEE
— One of the critical goals in code optimization for MPSoC architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely cos...
159
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SIGIR
2010
ACM
15 years 10 months ago
2010
ACM
This paper presents a novel prototype hierarchy based clustering (PHC) framework for the organization of web collections. It solves simultaneously the problem of categorizing web ...
179
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PPOPP
2012
ACM
14 years 1 months ago
2012
ACM
Analysis of massive graphs has emerged as an important area for massively parallel computation. In this paper, it is shown how the Fresh Breeze trees-of-chunks memory model may be...
282
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CISIS
2010
IEEE
14 years 9 months ago
2010
IEEE
Work-stealing is the todays algorithm of choice for dynamic load-balancing of irregular parallel applications on multiprocessor systems. We have evaluated the algorithm’s effic...
146
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HPCA
2005
IEEE
16 years 6 months ago
2005
IEEE
Memory system optimizations have been well studied on single-threaded systems; however, the wide use of simultaneous multithreading (SMT) techniques raises questions over their ef...