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ICPP
1999
IEEE
15 years 10 months ago
Improving Performance of Load-Store Sequences for Transaction Processing Workloads on Multiprocessors
On-line transaction processing exhibits poor memory behavior in high-end multiprocessor servers because of complex sharing patterns and substantial interaction between the databas...
Jim Nilsson, Fredrik Dahlgren
ARC
2010
Springer
144views Hardware» more  ARC 2010»
16 years 29 days ago
QUAD - A Memory Access Pattern Analyser
In this paper, we present the Quantitative Usage Analysis of Data (QUAD) tool, a sophisticated memory access tracing tool that provides a comprehensive quantitative analysis of mem...
S. Arash Ostadzadeh, Roel Meeuws, Carlo Galuzzi, K...
MICRO
2009
IEEE
134views Hardware» more  MICRO 2009»
16 years 24 days ago
Coordinated control of multiple prefetchers in multi-core systems
Aggressive prefetching is very beneficial for memory latency tolerance of many applications. However, it faces significant challenges in multi-core systems. Prefetchers of diff...
Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, Yale N....
ICRA
1995
IEEE
130views Robotics» more  ICRA 1995»
15 years 9 months ago
Improving the Response of SMA Actuators
Shape memory alloy (SMA) based actuators have a number of attributes which make them useful for robotic applications. Unfortunately their response is relatively slow, being limite...
R. Andrew Russell, Robert B. Gorbet
IEEEPACT
1999
IEEE
15 years 10 months ago
Memory System Support for Image Processing
Image processing applications tend to access their data non-sequentially and reuse that data infrequently. As a result, they tend to perform poorly on conventional memory systems ...
Lixin Zhang, John B. Carter, Wilson C. Hsieh, Sall...