1001 search results - page 53 / 201 » Improving memory hierarchy performance for irregular applica... |
202
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ISPASS
2010
IEEE
15 years 8 months ago
2010
IEEE
Abstract—Transactional memory promises to generalize transactional programming to mainstream languages and data structures. The purported benefit of transactions is that they ar...
191
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ASPDAC
2004
ACM
15 years 11 months ago
2004
ACM
— For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the instruction memory of embedded processors. In particular, software controlled ...
185
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CASES
2010
ACM
15 years 4 months ago
2010
ACM
Dynamic binary translators (DBTs) are becoming increasingly important because of their power and flexibility. However, the high memory demands of DBTs present an obstacle for all ...
158
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MICRO
2009
IEEE
16 years 24 days ago
2009
IEEE
Despite flash memory’s promise, it suffers from many idiosyncrasies such as limited durability, data integrity problems, and asymmetry in operation granularity. As architects, ...
196
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DAC
1999
ACM
16 years 7 months ago
1999
ACM
In embedded system design, the designer has to choose an onchip memory configuration that is suitable for a specific application. To aid in this design choice, we present a memory...