1001 search results - page 9 / 201 » Improving memory hierarchy performance for irregular applica... |
IPPS
2007
IEEE
14 years 3 months ago
2007
IEEE
— Modern CPUs operate at GHz frequencies, but the latencies of memory accesses are still relatively large, in the order of hundreds of cycles. Deeper cache hierarchies with large...
IPPS
1999
IEEE
14 years 1 months ago
1999
IEEE
Software distributed shared memory (DSM) systems have successfully provided the illusion of shared memory on distributed memory machines. However, most software DSM systems use th...
GLVLSI
2008
IEEE
14 years 3 months ago
2008
IEEE
Phase-based tuning methodologies specialize system parameters for each application phase of execution. Parameters are varied during execution, as opposed to remaining fixed as in ...
DAC
2002
ACM
14 years 9 months ago
2002
ACM
One of the primary challenges in embedded system design is designing the memory hierarchy and restructuring the application to take advantage of it. This task is particularly impo...
ICS
2005
Tsinghua U.
14 years 2 months ago
2005
Tsinghua U.
Supercomputer architects strive to maximize the performance of scientific applications. Unfortunately, the large, unwieldy nature of most scientific applications has lead to the...