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ASPDAC
2007
ACM
137views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Delay Uncertainty Reduction by Interconnect and Gate Splitting
Traditional timing variation reduction techniques are only able to decrease the gate delay variation by incurring a delay overhead. In this work, we propose novel and effective sp...
Vineet Agarwal, Jin Sun, Alexander V. Mitev, Janet...
FPGA
2008
ACM
168views FPGA» more  FPGA 2008»
13 years 8 months ago
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs
The Field Programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an ...
Alessandro Cevrero, Panagiotis Athanasopoulos, Had...
ICC
2008
IEEE
123views Communications» more  ICC 2008»
14 years 2 months ago
Downlink OFDM Scheduling and Resource Allocation for Delay Constraint SVC Streaming
Abstract—Efficient delivery of multimedia contents over wireless network is essential for future communication networks. However, content distribution and network engineering ar...
Xin Ji, Jianwei Huang, Mung Chiang, Francky Cattho...
FPGA
2008
ACM
131views FPGA» more  FPGA 2008»
13 years 9 months ago
WireMap: FPGA technology mapping for improved routability
This paper presents a new technology mapper, WireMap. The mapper uses an edge flow heuristic to improve the routability of a mapped design. The heuristic is applied during the ite...
Stephen Jang, Billy Chan, Kevin Chung, Alan Mishch...
ISQED
2007
IEEE
162views Hardware» more  ISQED 2007»
14 years 2 months ago
Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
David Zaretsky, Gaurav Mittal, Robert P. Dick, Pri...