271 search results - page 18 / 55 » Improving the Average Delay of Sorting |
DAC
2008
ACM
14 years 8 months ago
2008
ACM
Due to skewed scaling of interconnect delay and cell delay with technology scaling, modern VLSI timing closure requires use of extensive buffer insertion. Inserting a large number...
GLOBECOM
2010
IEEE
13 years 5 months ago
2010
IEEE
In current peer-to-peer file sharing networks, a large number of peers with heterogeneous connections simultaneously seek to download resources, e.g., files or file fragments, from...
GLOBECOM
2007
IEEE
14 years 2 months ago
2007
IEEE
A theoretical analysis for evaluating the performance of a lincoded continuous phase optical frequency shift keying (CPFSK) optical transmission system with delay line demodulation...
DATE
2003
IEEE
14 years 1 months ago
2003
IEEE
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...