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DATE
2006
IEEE
108views Hardware» more  DATE 2006»
14 years 1 months ago
Lens aberration aware timing-driven placement
Process variations due to lens aberrations are to a large extent systematic, and can be modeled for purposes of analyses and optimizations in the design phase. Traditionally, vari...
Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qi...
APCSAC
2005
IEEE
14 years 1 months ago
Energy-Effective Instruction Fetch Unit for Wide Issue Processors
Continuing advances in semiconductor technology and demand for higher performance will lead to more powerful, superpipelined and wider issue processors. Instruction caches in such ...
Juan L. Aragón, Alexander V. Veidenbaum
MSN
2005
Springer
14 years 1 months ago
Dual Binding Update with Additional Care of Address in Network Mobility
In this paper, we propose an end-to-end route optimization scheme for nested mobile networks, which we refer to as Dual Binding Update (DBU ). In general, the nested mobile network...
Kwang Chul Jeong, Tae-Jin Lee, Hyunseung Choo
DATE
2010
IEEE
171views Hardware» more  DATE 2010»
14 years 25 days ago
Power consumption of logic circuits in ambipolar carbon nanotube technology
Ambipolar devices have been reported in many technologies, including carbon nanotube field effect transistors (CNTFETs). The ambipolarity can be in-field controlled with a secon...
M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De ...
IPPS
1998
IEEE
14 years 4 hour ago
Impact of Switch Design on the Application Performance of Cache-Coherent Multiprocessors
In this paper, the effect of switch design on the application performance of cache-coherent non-uniform memory access (CC-NUMA) multiprocessors is studied in detail. Wormhole rout...
Laxmi N. Bhuyan, Hu-Jun Wang, Ravi R. Iyer, Akhile...