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CASES
2010
ACM
15 years 2 months ago
Balancing memory and performance through selective flushing of software code caches
Dynamic binary translators (DBTs) are becoming increasingly important because of their power and flexibility. However, the high memory demands of DBTs present an obstacle for all ...
Apala Guha, Kim M. Hazelwood, Mary Lou Soffa
GLOBECOM
2010
IEEE
15 years 2 months ago
Performance Analysis of Dynamic Spectrum Access Networks under Primary User Emulation Attacks
Primary user emulation attack (PUEA) is a denial of service (DoS) attack unique to dynamic spectrum access (DSA) networks. While there have been studies in the literature to detect...
Z. Jin, S. Anand, K. P. Subbalakshmi
TVLSI
2010
14 years 11 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...
INFOCOM
2010
IEEE
15 years 3 months ago
Analyzing the Performance of Greedy Maximal Scheduling via Local Pooling and Graph Theory
—Efficient operation of wireless networks and switches requires using simple (and in some cases distributed) scheduling algorithms. In general, simple greedy algorithms (known a...
Berk Birand, Maria Chudnovsky, Bernard Ries, Paul ...
ISCA
2010
IEEE
237views Hardware» more  ISCA 2010»
15 years 3 months ago
High performance cache replacement using re-reference interval prediction (RRIP)
Practical cache replacement policies attempt to emulate optimal replacement by predicting the re-reference interval of a cache block. The commonly used LRU replacement policy alwa...
Aamer Jaleel, Kevin B. Theobald, Simon C. Steely J...