122 search results - page 23 / 25 » In Situ Design of Register Operations |
FPGA
2010
ACM
13 years 9 months ago
2010
ACM
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
DSN
2009
IEEE
14 years 4 months ago
2009
IEEE
The threat of soft error induced system failure in high performance computing systems has become more prominent, as we adopt ultra-deep submicron process technologies. In this pap...
IMC
2004
ACM
14 years 3 months ago
2004
ACM
Accurate, reliable timestamping which is also convenient and inexpensive is needed in many important areas including real-time network applications and network measurement. Recent...
PLDI
2004
ACM
14 years 3 months ago
2004
ACM
When vectorizing for SIMD architectures that are commonly employed by today’s multimedia extensions, one of the new challenges that arise is the handling of memory alignment. Pr...
ISCA
2003
IEEE
14 years 2 months ago
2003
IEEE
To achieve high instruction throughput, instruction schedulers must be capable of producing high-quality schedules that maximize functional unit utilization while at the same time...