— We propose a low-leakage register file cell design based on the observation that the physical registers in a superscalar processor have very short life cycles. When a register...
Lingling Jin, Wei Wu, Jun Yang 0002, Chuanjun Zhan...
In this paper, we present a novel mechanism that implements register renaming, dynamic speculation and precise interrupts. Renaming of registers is performed during the instructio...
A model is presented for the analysis of bioremediation applied to an ex situ soil pile. The approach is based on the remediation of a pile containing the contaminated soil, which...
Conventional out-of-order processors that use a unified physical register file allocate and reclaim registers explicitly using a free list that operates as a circular queue. We ...
Steven Battle, Andrew D. Hilton, Mark Hempstead, A...
In high-level synthesis, as for compilers, an important question is when register assignment should take place. Unlike compilers for which the processor architecture is given, syn...