309 search results - page 24 / 62 » In-Network Cache Coherence |
AINA
2009
IEEE
14 years 2 months ago
2009
IEEE
This paper presents a modeling method particularly suited to analyze interactions between Message Passing Interface MPI library execution and distributed cache coherence protocol....
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
A key challenge in architecting a CMP with many cores is maintaining cache coherence in an efficient manner. Directory-based protocols avoid the bandwidth overhead of snoop-based ...
DSD
2009
IEEE
13 years 11 months ago
2009
IEEE
Modern systems are able to put two or more processors on the same die (Chip Multiprocessors, CMP), each with its private caches, while the last level caches can be either private ...
ISCA
1995
IEEE
13 years 11 months ago
1995
IEEE
This paper introduces dynamic self-invalidation (DSI), a new technique for reducing cache coherence overhead in shared-memory multiprocessors. DSI eliminates invalidation messages...
ANSS
1995
IEEE
13 years 11 months ago
1995
IEEE
In this paper we present simulation algorithmsthat characterize the main sources of communication generated by parallel applications under both invalidate and updatebased cache co...