661 search results - page 1 / 133 » Increasing Processor Performance by Implementing Deeper Pipe... |
ISCA
2002
IEEE
14 years 8 days ago
2002
IEEE
One architectural method for increasing processor performance involves increasing the frequency by implementing deeper pipelines. This paper will explore the relationship between ...
ICCD
2003
IEEE
14 years 4 months ago
2003
IEEE
Modern processors rely heavily on broadcast networks to bypass instruction results to dependent instructions in the pipeline. However, as clock rates increase, architectures get w...
IPPS
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper presents performance results for the design and implementation of parallel pipelined Space-Time Adaptive Processing (STAP) algorithms on parallel computers. In particul...
FPL
2007
Springer
14 years 1 months ago
2007
Springer
Designers of FPGA-based systems are increasingly including soft processors—processors implemented in programmable logic—in their designs. Any combination of area, clock freque...
JUCS
2007
13 years 7 months ago
2007
: This article presents an architecture that encrypts data with the AES algorithm. This architecture can be implemented on the Xilinx Virtex II FPGA family, by applying pipelining ...