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ISCA
1998
IEEE
151views Hardware» more  ISCA 1998»
13 years 11 months ago
Alternative Implementations of Two-Level Adaptive Branch Prediction
As the issue rate and depth of pipelining of high performance Superscalar processors increase, the importance of an excellent branch predictor becomes more vital to delivering the...
Tse-Yu Yeh, Yale N. Patt
MICRO
2007
IEEE
150views Hardware» more  MICRO 2007»
14 years 1 months ago
Leveraging 3D Technology for Improved Reliability
Aggressive technology scaling over the years has helped improve processor performance but has caused a reduction in processor reliability. Shrinking transistor sizes and lower sup...
Niti Madan, Rajeev Balasubramonian
ISCA
2002
IEEE
108views Hardware» more  ISCA 2002»
14 years 9 days ago
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays
Microprocessor clock frequency has improved by nearly 40% annually over the past decade. This improvement has been provided, in equal measure, by smaller technologies and deeper p...
M. S. Hrishikesh, Doug Burger, Stephen W. Keckler,...
DATE
2007
IEEE
100views Hardware» more  DATE 2007»
13 years 7 months ago
A new pipelined implementation for minimum norm sorting used in square root algorithm for MIMO-VBLAST systems
Multiple Input - Multiple Output (MIMO) wireless technology involves highly complex vectors and matrix computations which are directly related to increased power and area consumpt...
Zahid Khan, Tughrul Arslan, John S. Thompson, Ahme...
CC
2000
Springer
134views System Software» more  CC 2000»
13 years 7 months ago
Pipelined Java Virtual Machine Interpreters
The performance of a Java Virtual Machine (JVM) interpreter running on a very long instruction word (VLIW) processor can be improved by means of pipelining. While one bytecode is i...
Jan Hoogerbrugge, Lex Augusteijn