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» Increasing the level of abstraction in FPGA-based designs
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ISLPED
2005
ACM
147views Hardware» more  ISLPED 2005»
14 years 1 months ago
System level power and performance modeling of GALS point-to-point communication interfaces
Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising ...
Koushik Niyogi, Diana Marculescu
DSN
2009
IEEE
14 years 2 months ago
Power supply induced common cause faults-experimental assessment of potential countermeasures
Fault-tolerant architectures based on physical replication of components are vulnerable to faults that cause the same effect in all replica. Short outages in a power supply shared...
Peter Tummeltshammer, Andreas Steininger
DATE
2010
IEEE
159views Hardware» more  DATE 2010»
14 years 16 days ago
A rapid prototyping system for error-resilient multi-processor systems-on-chip
—Static and dynamic variations, which have negative impact on the reliability of microelectronic systems, increase with smaller CMOS technology. Thus, further downscaling is only...
Matthias May, Norbert Wehn, Abdelmajid Bouajila, J...
DATE
2003
IEEE
123views Hardware» more  DATE 2003»
14 years 22 days ago
RTOS Modeling for System Level Design
System level synthesis is widely seen as the solution for closing the productivity gap in system design. High level system models are used in system level design for early design ...
Andreas Gerstlauer, Haobo Yu, Daniel Gajski
ICSE
2004
IEEE-ACM
14 years 7 months ago
Assume-Guarantee Verification of Source Code with Design-Level Assumptions
Model checking is an automated technique that can be used to determine whether a system satisfies certain required properties. To address the "state explosion" problem a...
Dimitra Giannakopoulou, Corina S. Pasareanu, Jamie...