452 search results - page 25 / 91 » Incremental formal design verification |
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Formal languages are increasingly used to describe the functional requirements (specifications) of circuits. These requirements are used as a means to communicate design intent an...
ENTCS
2006
13 years 7 months ago
2006
Effective formal verification tools require that robust implementations of automatic procedures for first-order logic and satisfiability modulo theories be integrated into express...
FMCAD
2007
Springer
13 years 11 months ago
2007
Springer
We present a framework for formal verification of embedded custom memories. Memory verification is complicated ifficulty in abstracting design parameters induced by the inherently ...
ISQED
2010
IEEE
13 years 9 months ago
2010
IEEE
We present a method to abstract, formalize, and verify industrial flash memory implementations. Flash memories contain specialized transistors, e.g., floating gate and split gate d...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
The design of a large chip is typically hierarchical