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» Incremental reconfiguration for pipelined applications
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ARC
2010
Springer
183views Hardware» more  ARC 2010»
13 years 10 months ago
Integrated Design Environment for Reconfigurable HPC
Using FPGAs to accelerate High Performance Computing (HPC) applications is attractive, but has a huge associated cost: the time spent, not for developing efficient FPGA code but fo...
Lilian Janin, Shoujie Li, Doug Edwards
FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
13 years 10 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
SSD
1995
Springer
97views Database» more  SSD 1995»
14 years 1 months ago
Ranking in Spatial Databases
Abstract. An algorithm for ranking spatial objects according to increasing distance from a query object is introduced and analyzed. The algorithm makes use of a hierarchical spatia...
Gísli R. Hjaltason, Hanan Samet
IVC
2006
123views more  IVC 2006»
13 years 9 months ago
Multi-sector algorithm for hardware acceleration of the general Hough transform
The Multi-Sector Algorithm (MSA) is a simplification of the CORDIC algorithm to more closely meet the requirements for a real-time general Hough transform applications. The MSA ca...
Emeric K. Jolly, Martin Fleury
DATE
2009
IEEE
149views Hardware» more  DATE 2009»
14 years 4 months ago
An ILP formulation for task mapping and scheduling on multi-core architectures
Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory a...
Ying Yi, Wei Han, Xin Zhao, Ahmet T. Erdogan, Tugh...