This paper presents a chip-level charged device model (CDM) electrostatic discharge (ESD) simulation method. The chip-level simulation is formulated as a DC analysis problem. A ne...
Haifeng Qian, Joseph N. Kozhaya, Sani R. Nassif, S...
A polynomial-time algorithm is presented for partitioning a collection of sporadic tasks among the processors of an identical multiprocessor platform with static-priority scheduli...
Nathan Fisher, Sanjoy K. Baruah, Theodore P. Baker
The partition function pertaining to finite–temperature decoding of a (typical) randomly chosen code is known to have three types of behavior, corresponding to three phases in ...
Abstract. Three simple and explicit procedures for testing the independence of two multi-dimensional random variables are described. Two of the associated test statistics (L1, log-...
Over the past decade, the steady growth rate of FPGA device capacities has enabled the development of multi-FPGA prototyping environments capable of implementing millions of logic...