The ultimate goal of logic synthesis is to explore implementation flexibility toward meeting design targets, such as area, power, and delay. Traditionally, such flexibility is exp...
The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling edges of...
Victor Khomenko, Maciej Koutny, Alexandre Yakovlev
Protocol conversion involves the use of a converter to control communication between two or more protocols such that desired system-level specifications can be satisfied. We invest...
This paper presents an automated analog synthesis tool for topology generation and subsequent circuit sizing. Though sizing is indispensable, the paper mainly concentrates on topo...
In this paper, our objective is to facilitate the creation of novel human poses by synthesizing images. Existing approaches commonly deform one single image, which often results i...
Cedric Vanaken, Chris Hermans, Tom Mertens, Fabian...