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ISCA
2008
IEEE
148views Hardware» more  ISCA 2008»
15 years 11 months ago
Atomic Vector Operations on Chip Multiprocessors
The current trend is for processors to deliver dramatic improvements in parallel performance while only modestly improving serial performance. Parallel performance is harvested th...
Sanjeev Kumar, Daehyun Kim, Mikhail Smelyanskiy, Y...
153
Voted
IPPS
2010
IEEE
15 years 3 months ago
Highly scalable parallel sorting
Sorting is a commonly used process with a wide breadth of applications in the high performance computing field. Early research in parallel processing has provided us with comprehen...
Edgar Solomonik, Laxmikant V. Kalé
145
Voted
HPCA
2001
IEEE
16 years 5 months ago
A New Scalable Directory Architecture for Large-Scale Multiprocessors
The memory overhead introduced by directories constitutes a major hurdle in the scalability of cc-NUMA architectures, which makes the shared-memory paradigm unfeasible for very la...
Manuel E. Acacio, José González, Jos...
SBACPAD
2007
IEEE
143views Hardware» more  SBACPAD 2007»
15 years 11 months ago
A Code Compression Method to Cope with Security Hardware Overheads
Code Compression has been used to alleviate the memory requirements as well as to improve performance and/or minimize energy consumption. On the other hand, implementing security ...
Eduardo Wanderley Netto, Romain Vaslin, Guy Gognia...
ATAL
2003
Springer
15 years 10 months ago
Authoring scenes for adaptive, interactive performances
In this paper, we introduce a toolkit called SceneMaker for authoring scenes for adaptive, interactive performances. These performances are based on automatically generated and pr...
Patrick Gebhard, Michael Kipp, Martin Klesen, Thom...