78 search results - page 3 / 16 » Instruction Cache Fetch Policies for Speculative Execution |
CASES
2001
ACM
13 years 11 months ago
2001
ACM
Abstract. Existing variable-length instruction formats provide higher code densities than fixed-length formats, but are ill-suited to pipelined or parallel instruction fetch and de...
MICRO
1998
IEEE
13 years 12 months ago
1998
IEEE
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
HPCA
2001
IEEE
14 years 8 months ago
2001
IEEE
Mispredicted branches and loads that miss in the cache cause the majority of retirement stalls experienced by sequential processors; we call these critical instructions. Despite t...
MICRO
1999
IEEE
13 years 12 months ago
1999
IEEE
Branch mispredictions can have a major performance impact on high-performance processors. Multipath execution has recently been introduced to help limit the misprediction penaltie...
MICRO
1993
IEEE
13 years 11 months ago
1993
IEEE
In this paper, we present a novel mechanism that implements register renaming, dynamic speculation and precise interrupts. Renaming of registers is performed during the instructio...