78 search results - page 7 / 16 » Instruction Cache Fetch Policies for Speculative Execution |
ISCA
2000
IEEE
14 years 2 hour ago
2000
IEEE
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...
IEEEPACT
1998
IEEE
13 years 12 months ago
1998
IEEE
Conventional speculative architectures use branch prediction to evaluate the most likely execution path during program execution. However, certain branches are difficult to predic...
IEEEINTERACT
2003
IEEE
14 years 27 days ago
2003
IEEE
Speculative pre-execution is a promising prefetching technique which uses an auxiliary assisting thread in addition to the main program flow. A prefetching thread (p-thread), whic...
ECRTS
2006
IEEE
14 years 1 months ago
2006
IEEE
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...