174 search results - page 27 / 35 » Instruction Fetch Mechanisms for Multipath Execution Process... |
MICRO
2007
IEEE
14 years 1 months ago
2007
IEEE
As silicon process technology scales deeper into the nanometer regime, hardware defects are becoming more common. Such defects are bound to hinder the correct operation of future ...
ISCA
2007
IEEE
14 years 1 months ago
2007
IEEE
Conventional load/store queues (LSQs) are an impediment to both power-efficient execution in superscalar processors and scaling to large-window designs. In this paper, we propose...
HIPEAC
2005
Springer
14 years 1 months ago
2005
Springer
Abstract. High end routers are targeted at providing worst case throughput guarantees over latency. Caches on the other hand are meant to help latency not throughput in a tradition...
ISCA
1998
IEEE
13 years 11 months ago
1998
IEEE
Modern processors improve instruction level parallelism by speculation. The outcome of data and control decisions is predicted, and the operations are speculatively executed and o...
MICRO
1995
IEEE
13 years 11 months ago
1995
IEEE
Untolerated load instruction latencies often have a significant impact on overall program performance. As one means of mitigating this effect, we present an aggressive hardware-b...