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HPCA
2000
IEEE
13 years 11 months ago
Impact of Chip-Level Integration on Performance of OLTP Workloads
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
Luiz André Barroso, Kourosh Gharachorloo, A...
ICDCN
2011
Springer
12 years 10 months ago
A High-Level Framework for Distributed Processing of Large-Scale Graphs
Distributed processing of real-world graphs is challenging due to their size and the inherent irregular structure of graph computations. We present HIPG, a distributed framework th...
Elzbieta Krepska, Thilo Kielmann, Wan Fokkink, Hen...
IPPS
2000
IEEE
13 years 11 months ago
Parallel Low-Level Image Processing on a Distributed-Memory System
The paper presents a method to integrate parallelism in the DIPLIB sequential image processing library. The library contains several framework functions for di erent types of opera...
Cristina Nicolescu, Pieter Jonker
HPCA
2006
IEEE
14 years 7 months ago
An approach for implementing efficient superscalar CISC processors
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
Shiliang Hu, Ilhyun Kim, Mikko H. Lipasti, James E...
HPCA
2004
IEEE
14 years 7 months ago
Understanding Scheduling Replay Schemes
Modern microprocessors adopt speculative scheduling techniques where instructions are scheduled several clock cycles before they actually execute. Due to this scheduling delay, sc...
Ilhyun Kim, Mikko H. Lipasti