2784 search results - page 10 / 557 » Instruction Level Parallelism |
CONCURRENCY
2006
13 years 9 months ago
2006
To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
DATE
2006
IEEE
14 years 3 months ago
2006
IEEE
This paper presents a new operation chaining reconfigurable scheduling algorithm (CRS) based on list scheduling that maximizes instruction level parallelism available in distribut...
EUROPAR
1999
Springer
14 years 2 months ago
1999
Springer
Growing demand for high performance in embedded systems is creating new opportunities for Instruction-Level Parallelism ILP techniques that are traditionally used in high perform...
DAC
2002
ACM
14 years 10 months ago
2002
ACM
Increasing non-recurring engineering (NRE) and mask costs are making it harder to turn to hardwired Application Specific Integrated Circuit (ASIC) solutions for high performance a...
SCAM
2005
IEEE
14 years 3 months ago
2005
IEEE
Most software for embedded systems, including digital signal processing systems, is coded in assembly language. For both understanding the software and for reverse compiling it to...