2784 search results - page 16 / 557 » Instruction Level Parallelism |
ISSS
1998
IEEE
14 years 2 months ago
1998
IEEE
Designing a cost effective superscalar architecture for x86 compatible microprocessors is a challenging task in terms of both technical difficulty and commercial value. One of the...
ISCA
1998
IEEE
14 years 2 months ago
1998
IEEE
Explicitly Parallel Instruction Computing (EPIC) architectures require the compiler to express program instruction level parallelism directly to the hardware. EPIC techniques whic...
IEEEPACT
2009
IEEE
14 years 4 months ago
2009
IEEE
With advances in hardware, instruction set architectures are undergoing continual evolution. As a result, compilers are under constant pressure to adapt and take full advantage of...
ISCAPDCS
2001
13 years 11 months ago
2001
This paper presents the evaluation of a non-blocking, decoupled memory/execution, multithreaded architecture known as the Scheduled Dataflow (SDF). The major recent trend in digit...
ISCA
1998
IEEE
14 years 2 months ago
1998
IEEE
Branch prediction has enabled microprocessors to increase instruction level parallelism (ILP) by allowing programs to speculatively execute beyond control boundaries. Although spe...