2784 search results - page 28 / 557 » Instruction Level Parallelism |
ISCA
2008
IEEE
14 years 4 months ago
2008
IEEE
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...
FPGA
2004
ACM
14 years 3 months ago
2004
ACM
We describe an effort to prototype an Itanium microarchitecture using an FPGA. The microarchitecture model is written in the Bluespec hardware description language (HDL) and suppo...
IEEEPACT
2006
IEEE
14 years 3 months ago
2006
IEEE
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
IISWC
2009
IEEE
14 years 4 months ago
2009
IEEE
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...
ICALT
2006
IEEE
14 years 3 months ago
2006
IEEE
The application of software engineering approaches to generate learning material adapted to a specific instructional purpose presents some issues: of different models, different a...