2784 search results - page 32 / 557 » Instruction Level Parallelism |
ICPPW
2006
IEEE
14 years 3 months ago
2006
IEEE
In retargeting loop-based code for multimedia instruction set extensions, a critical issue is that vector data types of mixed precision within a loop body complicate the paralleli...
ICS
2007
Tsinghua U.
14 years 4 months ago
2007
Tsinghua U.
This paper explores the scalability of the Stream Processor architecture along the instruction-, data-, and thread-level parallelism dimensions. We develop detailed VLSI-cost and ...
EUROPAR
2001
Springer
14 years 2 months ago
2001
Springer
ASAP
2007
IEEE
14 years 4 months ago
2007
IEEE
Existing SIMD extensions cannot efficiently vectorize the histogram function due to memory collisions. We propose two techniques to avoid this problem. In the first, a hierarchi...
JAR
2006
13 years 9 months ago
2006
We describe an approach to verifying bit-level pipelined machine models using a combination of deductive reasoning and decision procedures. While theorem proving systems such as AC...